Methods of fabricating interconnection structures
US9202744B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an interconnection structure according to an embodiment of the present invention, includes patterning a dielectric layer to form a first recession region, including a first nest-shaped recession region having a first width and a first line-shaped recession region having a second width, which is less than the first width. A guide spacer layer is formed on sidewalls of the first recession region to provide a second recession region including a second nest-shaped recession region in the first nest-shaped recession region. A self-assembling block copolymer material is formed to fill the second nest-shaped recession region. The self-assembling block copolymer material is annealed to form a polymer block domain and a polymer block matrix, surrounding the polymer block domain. The polymer block domain is removed to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is etched to form a via cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.