Integrated circuits with improved gap fill dielectric and methods for fabricating same
US9202746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jan 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.