Patent · US Active

Apparatus and method for reducing leakage power of a circuit

US9207750B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Gururaj K. Shamanna · Austin, US
Stefan Rusu · Sunnyvale, US
Phani Kumar Kandula · Bengaluru, IN
Sankalan Prasad · Bengaluru, IN
Mandar R. Ranade · Bengaluru, IN
Narayanan Natarajan · Marlboro, US
Tessil Thomas · Bengaluru, IN

Key dates

Filing date	Dec 14, 2012
Grant date	Dec 8, 2015
Priority date	—
Expiry date	Nov 14, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.