Sequential memory operation without deactivating access line signals
US9208833B2 · kind B2 · utility
10Cited by
4References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 23, 2013 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Sep 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.