Low power static random access memory (SRAM) read data path
US9208859B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Aug 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit configured for reducing dynamic read power is disclosed that includes a first read global bit line connected to a first sense amp and a second read global bit line connected to a second sense amp. The second read global bit line is adjacent to the first read global bit line. The memory circuit further includes a third read global bit line and logic circuitry connected to the first read global bit line, the second read global bit line, and the third read global bit line. The logic circuitry is configured to determine when both the first read global bit line and the second read global bit line are evaluated as in a high state, and in response to the determining, toggle the third read global bit line to the high state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.