Patent · US Active

Semiconductor package with lead mounted power bar

US9209120B2 · kind B2 · utility

0Cited by

16References

14Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Kong Bee Tiu · Port Klang, MY
Chee Seng Foong · Bandar Baru Sungai Buloh, MY
Wai Yew Lo · Petaling Jaya, MY

Key dates

Filing date	Mar 11, 2014
Grant date	Dec 8, 2015
Priority date	—
Expiry date	Jul 19, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19107
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor package includes a lead frame having an interior region and leads surrounding the interior region, an integrated circuit, a region of insulating material, and a power bar. The integrated circuit, which is disposed in the interior region, has bond pads and electrical couplings (e.g., bond wires) between the bond pads and the leads. The region of insulating material is disposed on at least some of the lead frame leads and the power bar is disposed on the region of insulating material. There also are electrical couplings between the power bar and at least some of the bond pads.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.