Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9209154B2 · kind B2 · utility
8Cited by
12References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Dec 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor package with package-on-package stacking capability is characterized by the step of attaching a chip-on-interposer subassembly on a base carrier with the chip inserted into a through opening of the base carrier and the interposer laterally extending beyond the through opening. The interposer provides primary fan-out routing for the chip whereas dual buildup circuitries formed on both opposite sides of the base carrier provides further fan-out routing and are electrically connected to each other by plated through holes to provide the package with stacking capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.