Methods for forming a self-aligned maskless junction butting for integrated circuits
US9209200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2013 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/075
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device includes forming gate stacks on a crystalline semiconductor layer; depositing a spacer layer over a top and sidewalls of the gate stacks; recessing the semiconductor layer between the gates stacks; and depositing a non-conformal layer over the gates stacks and within the recesses such that the non-conformal layer forms a pinch point over the recesses. The non-conformal layer is etched at a bottom of the recesses through the pinch point to expose the semiconductor layer. Dopant species are implanted at the bottom of the recesses through the pinch point in the semiconductor layer. The non-conformal layer is stripped, and source and drain material is grown in the recesses. The dopant species are activated to form PN junctions to act as a junction butt between portions of the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.