Replacement source/drain finFET fabrication
US9209278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Mar 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.