Ratioless near-threshold level translator
US9209810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Jun 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.