Vertical 4-way shared pixel in a single column with internal reset and no row select
US9210347B2 · kind B2 · utility
2Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2013 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Feb 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/813
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.