Reset generation circuit for scan mode exit
US9213063B2 · kind B2 · utility
3Cited by
5References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A reset generation circuit of an integrated circuit uses a scan data input pin as a scan mode exit control, which is enabled only when the IC reset pin of the device is active. The reset generation circuit allows a TAP controller to be scan testable yet at the same time the circuit provides a method to exit scan mode without requiring a power-up sequence or an extra pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.