Controller to manage NAND memories
US9213603B2 · kind B2 · utility
9Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Aug 11, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.