Methods of patterning features having differing widths
US9214360B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 1, 2013 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Jun 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.