Method of semiconductor integrated circuit fabrication
US9214383B2 · kind B2 · utility
2Cited by
0References
20Claims
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Assignee
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Key dates
| Filing date | Jan 18, 2013 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | May 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.