Transistor with embedded stress-inducing layers

US9214396B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stefan Flachowsky · Dresden, DE
• Jan Hoentschel · Dresden, DE
• Gerd Zschaetzsch · Dresden, DE

Key dates

• Filing date: Jun 3, 2014
• Grant date: Dec 15, 2015
• Expiry date: Jun 3, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/62
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.