Patent · US Active

Stack packages and methods of fabricating the same

US9214410B2 · kind B2 · utility

17Cited by
2References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 4, 2014
Grant dateDec 15, 2015
Priority date—
Expiry dateApr 4, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/15311
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.