Fan-out semiconductor package
US9214434B1 · kind B1 · utility
54Cited by
4References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.