Memory cell structure and formation method thereof
US9214495B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Sep 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
Abstract
A memory cell structure is provided. A first doping region is formed in a substrate. A second doping region is formed in the substrate. A first gate is formed on the substrate. The first and second doping regions and the first gate constitute a first transistor. A first word line is electrically connected to the first gate. The first word line firstly extends along a first direction and then along a second direction which is different from the first direction. A resistive layer is electrically connected to the first doping region. A conductive layer comprises a first source line and a bit line. The first source line is electrically connected to the second doping region, and the bit line is electrically connected to the resistive layer. The first and second doping regions extend along a third direction which is different from the first and second directions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.