Response to tamper detection in a memory device
US9218509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Feb 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.