Patent · US Active

Method of manufacturing a semiconductor device including a stress relief layer

US9218960B2 · kind B2 · utility

2Cited by

1References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Nelle · Munich, DE
Uwe Schmalzbauer · Neubiberg, DE
Juergen Holzmueller · Reichenbach/Oberlausitz, DE
Markus Zundel · Egmating, DE

Key dates

Filing date	Jun 30, 2014
Grant date	Dec 22, 2015
Priority date	—
Expiry date	Jun 30, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a Young's modulus greater than 10 GPa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower Young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.