Double self aligned via patterning
US9219007B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 10, 2013 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Oct 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76898
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.