Patent · US Active

Chip arrangement, and method for forming a chip arrangement

US9219031B2 · kind B2 · utility

0Cited by

1References

31Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Ossimitz · Munich, DE
Robert Bauer · San Diego, US
Tobias Jacobs · Mannheim, DE

Key dates

Filing date	May 13, 2013
Grant date	Dec 22, 2015
Priority date	—
Expiry date	Oct 14, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/381
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.