3-D memory arrays

US9219070B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Deepak Thimmegowda · Fremont, US
• Brian Cleereman · Boise, US
• Khaled Hasnat · San Jose, US

Key dates

• Filing date: Feb 5, 2013
• Grant date: Dec 22, 2015
• Expiry date: Jul 23, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/693

Abstract

A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.