LDMOS with improved breakdown voltage
US9219147B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | May 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.