Performance and memory efficient modeling of HDL ports for simulation
US9223910B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2014 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.