Method and apparatus for VT invariant SDRAM write leveling and fast rank switching
US9224444B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.