Techniques for detection and treating memory hole to local interconnect marginality defects
US9224502B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2015 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Jan 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented for the determination and handling of defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defects, an AC stress can be applied between the interconnects and the bit lines/NAND strings, after which a defect determination operation can be performed. This technique can also be implemented at the system level by having the controller instruct the memory to perform it as part of an adaptive defect determination operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.