Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
US9224674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2011 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.