Substrate for semiconductor package and process for manufacturing
US9224707B2 · kind B2 · utility
1Cited by
66References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2014 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Oct 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.