Lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a below source isolation region and a method of forming the LDMOSFET
US9224858B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2014 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Jul 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a field effect transistor (FET) (e.g., a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET)) and a method of forming the FET. In the FET, an etch stop pad is on a semiconductor substrate (e.g., a P-type silicon substrate). A semiconductor layer (e.g., a silicon layer) is also on the substrate and extends laterally over the etch stop pad. A first well region (e.g., an N-well region) extends through the semiconductor layer into the substrate such that it contains the etch stop pad. A second well region (e.g., a P-well region) is in the first well region aligned above the etch stop pad. A source region (e.g., a N-type source region) is in the second well region. A buried isolation region (e.g., a buried air-gap isolation region) is within the first well region aligned below the etch stop pad so as to limit vertical capacitor formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.