Integrated circuit with degradation monitoring
US9229051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2012 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Nov 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.