Memory controller with transaction-queue-dependent power modes
US9229523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2015 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Apr 23, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.