Internal plasma grid applications for semiconductor fabrication in context of ion-ion plasma processing

US9230819B2 · kind B2 · utility

Assignee

• Lam Research Corporation · US

Inventors

• Alex Paterson · San Jose, US
• Do-Young Kim · Paju-si, KR
• Gowri Kamarthy · Pleasanton, US
• Helene Del Puppo · Fremont, US
• Jen-Kan Yu · Fremont, US
• Monica Titus · Santa Clara, US
• Radhika Mani · Fremont, US
• Noel Sun · Sunnyvale, US
• Nicolas Gani · Milpitas, US
• Yoshie Kimura · Castro Valley, US
• Ting-Ying Chung · Fremont, US

Key dates

• Filing date: Feb 19, 2014
• Grant date: Jan 5, 2016
• Expiry date: Feb 19, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76224
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.