Three-dimensional chip stack for self-powered integrated circuit
US9230940B2 · kind B2 · utility
12Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Oct 26, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and methods for self-powered devices are disclosed herein. Specifically, disclosed herein is a stacked, three-dimensional integrated circuit including a power generation die including a power source. The integrated circuit also includes a functional system die including one or more functional components that are powered by power generated by the power source. The power generation die and the functional system die are stacked in a three-dimensional structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.