Protective structure to prevent short circuits in a three-dimensional memory device
US9230982B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2014 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.