Hybrid CMOS nanowire mesh device and FINFET device
US9230989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2014 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Mar 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.