Bias to detect and prevent short circuits in three-dimensional memory device
US9236131B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.