Wafer, a method for processing a wafer, and a method for processing a carrier
US9236241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | May 10, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/13
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to various embodiments, a method for processing a wafer may include: forming at least one hollow chamber and a support structure within the wafer, the at least one hollow chamber defining a cap region of the carrier located above the at least one hollow chamber and a bottom region of the carrier located below the at least one hollow chamber and an edge region surrounding the cap region of the carrier, wherein a surface area of the cap region is greater than a surface area of the edge region, and wherein the cap region is connected to the bottom region by the support structure; removing the cap region in one piece from the bottom region and the edge region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.