Three dimensional NAND device and method of making thereof
US9236396B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Nov 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.