Nonvolatile memory structure and fabrication method thereof
US9236453B2 · kind B2 · utility
3Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Mar 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.