AC stress methods to screen out bit line defects
US9240249B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2014 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A number of techniques for determining bit line related defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Defects related to bit line to NAND string contacts are determined by application of an AC stress mode along bit lines, followed by a defect detection operation. If the AC stress is applied to be out of phase on adjacent bit lines, this can also be used to accelerate bit line to bit line defects. The subsequent defect determination phase can include an erase operation followed a read to determine whether the NAND strings of the erased block read as erased, a process that can also be followed by a program and subsequent read to further check for defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.