Method minimizing imprint through packaging of F-RAM
US9240440B1 · kind B1 · utility
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3References
15Claims
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Key dates
| Filing date | Jun 21, 2013 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Feb 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of minimizing imprint in a ferroelectric capacitor uses a gradually attenuated AC field to electrically depolarize the ferroelectric capacitor before being packaged. The AC field is linearly attenuated, and generated using a series of voltage pulses, down to a minimum allowed voltage. A final pulse is a positive voltage to minimize hydrogen degradation during packaging. Thermal depoling can also be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.