Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs

US9244124B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rodrigo Alvarez-Icaza Rivera · San Jose, US
• John V. Arthur · Mountain View, US
• Andrew S. Cassidy · San Jose, US
• Bryan L. Jackson · Fremont, US
• Paul A. Merolla · Palo Alto, US
• Dharmendra S. Modha · San Jose, US
• Jun Sawada · Austin, US

Key dates

• Filing date: Mar 28, 2014
• Grant date: Jan 26, 2016
• Expiry date: Jul 17, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3187
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.