Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9244686B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2012 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Apr 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.