Methods, apparatus and system for reduction of power consumption in a semiconductor device
US9245087B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Aug 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.