Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
US9245790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2013 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jan 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.