Patent · US Active

Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance

US9245813B2 · kind B2 · utility

10Cited by
27References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 30, 2013
Grant dateJan 26, 2016
Priority date
Expiry dateJan 30, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.