RRAM process with metal protection layer
US9245925B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2015 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jan 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming an insulation layer on an access device followed by forming vias through the insulation layer to expose the first and second access device terminals. First and second interlayer conductors extending through the vias are formed next. Top surfaces of the interlayer conductors are oxidized to form oxide layers. The oxide layer on the first interlayer conductor forms a memory layer. On top of the insulation layer a layer of protection metal is formed covering the oxide layers. The layer of protection metal is patterned and etched to form a top electrode layer covering the memory layer. The oxide layer on the second interlayer conductor is removed. Parallel first and second access lines are then formed on the top electrode layer and the second interlayer conductor, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.