Lateral double-diffused metal-oxide-semiconudctor transistor device and layout pattern for LDMOS transistor device
US9245996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jun 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.